Question 1

A 30 kHz clock pulse is applied to a MOD- 15 ripple counter. What is the output frequency?

Accepted Answer

A)  2.5 kHz 
B)  1.55 kHz 
C)  2 kHz 
D)  1.88 kHz 
A)  2.5 kHz 
B)  1.55 kHz 
C)  2 kHz 
D)  1.88 kHz

Question 2

A MOD 12 and a MOD 10 counter are cascaded. The input clock frequency is 60 MHz. Determine the counter output frequency.

Accepted Answer

A)  1,500 kHz 
B)  6 MHz 
C)  5 MHz 
D)  500 kHz 
A)  1,500 kHz 
B)  6 MHz 
C)  5 MHz 
D)  500 kHz

Question 3

-Select the sequence for the counter in Figure 7- 1 that best describes its operation.

Accepted Answer

A)  Counter clears: starts counting pulses when the sample pulse goes HIGH; stops counting when the sample pulse goes LOW. Clear pulse clears the counter by transferring its contents into the decoder/display unit. 
B)  Counter clears: starts counting pulses when the sampling pulse goes LOW; stops counting when the sampling pulse goes LOW; stops counting when the sample pulse goes LOW and displays the final count. 
C)  Counter clears: starts counting pulses when the sampling pulse goes HIGH; displays the counts as they occur and stop counting when the sampling pulse goes LOW. Count is displayed until the counter is cleared. 
D)  Counter clears: starts counting pulses when the sample pulse goes HIGH; stops counting when the sample pulse goes LOW. The LOW sample pulse activates the display and the final count is displayed. 
A)  Counter clears: starts counting pulses when the sample pulse goes HIGH; stops counting when the sample pulse goes LOW. Clear pulse clears the counter by transferring its contents into the decoder/display unit. 
B)  Counter clears: starts counting pulses when the sampling pulse goes LOW; stops counting when the sampling pulse goes LOW; stops counting when the sample pulse goes LOW and displays the final count. 
C)  Counter clears: starts counting pulses when the sampling pulse goes HIGH; displays the counts as they occur and stop counting when the sampling pulse goes LOW. Count is displayed until the counter is cleared. 
D)  Counter clears: starts counting pulses when the sample pulse goes HIGH; stops counting when the sample pulse goes LOW. The LOW sample pulse activates the display and the final count is displayed.

Question 4

When two counters are cascaded, the overall MOD number is equal to the____of their individual MOD numbers

Accepted Answer

The answer of When two counters are cascaded, the overall...

Question 5

MOD number = 2n, where n = number of flip- flops.

Accepted Answer

A) True 
 B)False

Question 6

-What will the display reading in Figure 7- 1 be if the sampling interval is 100 ms and the unknown frequency is 200 kHz? (Assume the counter was cleared prior to the sampling interval.)

Accepted Answer

A)  15,000 
B)  20,000 
C)  5,000 
D)  10,000 
A)  15,000 
B)  20,000 
C)  5,000 
D)  10,000

Question 7

-The "CLEAR" input in Figure 7- 1:

Accepted Answer

A)  requires a HIGH input and is used as the initial clock pulse input for the counting operation. 
B)  requires a HIGH input and is used to clear the counter before the sampling interval begins. 
C)  requires a LOW input and is used to clear the counter before the sampling interval begins. 
D)  requires a LOW input and is used as the initial clock pulse for the counting operation. 
A)  requires a HIGH input and is used as the initial clock pulse input for the counting operation. 
B)  requires a HIGH input and is used to clear the counter before the sampling interval begins. 
C)  requires a LOW input and is used to clear the counter before the sampling interval begins. 
D)  requires a LOW input and is used as the initial clock pulse for the counting operation.

Question 8

Typically, four flip- flops are required for a MOD- 60 counter.

Accepted Answer

A) True 
 B)False

Question 9

The + sign on a counter symbol by the input labeled CP indicates a count- up operation.

Accepted Answer

A) True 
 B)False

Question 10

Table 7- 1   Table 7- 1 shows a state sequence used to program a GAL16V as a counter. The indicated sequence represents a:

Accepted Answer

A)  BCD counter. 
B)  Johnson counter. 
C)  ring counter. 
D)  binary counter. 
A)  BCD counter. 
B)  Johnson counter. 
C)  ring counter. 
D)  binary counter.

Question 11

Asynchronous down counters:

Accepted Answer

A)  require that the LSB flip- flop change states with each input clock pulse the same as an up counter. 
B)  require that the MSB and LSB flip- flops change states with each input clock pulse. 
C)  require that the MSB flip- flop change states with each input clock pulse the same as an up counter. 
D)  require that each flip- flop change states with each input clock pulse. 
A)  require that the LSB flip- flop change states with each input clock pulse the same as an up counter. 
B)  require that the MSB and LSB flip- flops change states with each input clock pulse. 
C)  require that the MSB flip- flop change states with each input clock pulse the same as an up counter. 
D)  require that each flip- flop change states with each input clock pulse.

Question 12

Shift registers that are identified as parallel in/parallel out, serial in/parallel out, etc. are defined in this manner because:

Accepted Answer

A)  it indicates the manner in which data are stored in the register. 
B)  it indicates the manner in which data can be entered into the register for storage and the manner in which data are outputted from the register. 
C)  it indicates the inverse of how data are entered into the register for storage and how data are outputted from the register. 
D)  Both A and C 
A)  it indicates the manner in which data are stored in the register. 
B)  it indicates the manner in which data can be entered into the register for storage and the manner in which data are outputted from the register. 
C)  it indicates the inverse of how data are entered into the register for storage and how data are outputted from the register. 
D)  Both A and C

Question 13

How many stages would be required for a cascaded BCD counter to provide a decimal count of 9,999?

Accepted Answer

A)  5 
B)  4 
C)  3 
D)  6 
A)  5 
B)  4 
C)  3 
D)  6

Question 14

A MOD- 4 counter with an input clock frequency of 1500 Hz has an output frequency of 375 Hz.

Accepted Answer

A) True 
 B)False

Question 15

A major advantage of the synchronous counter over the nonsynchronous counter is its ability to:

Accepted Answer

A)  operate at lower frequencies. 
B)  operate with its J- K inputs tied permanently HIGH. 
C)  operate at higher frequencies. 
D)  operate with no external circuitry. 
A)  operate at lower frequencies. 
B)  operate with its J- K inputs tied permanently HIGH. 
C)  operate at higher frequencies. 
D)  operate with no external circuitry.

A 30 kHz clock pulse is applied to a MOD- 15 ripple counter. What is the output frequency?

A MOD 12 and a MOD 10 counter are cascaded. The input clock frequency is 60 MHz. Determine the counter output frequency.

-Select the sequence for the counter in Figure 7- 1 that best describes its operation.

When two counters are cascaded, the overall MOD number is equal to the____of their individual MOD numbers

MOD number = 2ⁿ, where n = number of flip- flops.

-What will the display reading in Figure 7- 1 be if the sampling interval is 100 ms and the unknown frequency is 200 kHz? (Assume the counter was cleared prior to the sampling interval.)

-The "CLEAR" input in Figure 7- 1:

Typically, four flip- flops are required for a MOD- 60 counter.

The + sign on a counter symbol by the input labeled CP indicates a count- up operation.

Table 7- 1 Table 7- 1 shows a state sequence used to program a GAL16V as a counter. The indicated sequence represents a:

Asynchronous down counters:

Shift registers that are identified as parallel in/parallel out, serial in/parallel out, etc. are defined in this manner because:

How many stages would be required for a cascaded BCD counter to provide a decimal count of 9,999?

A MOD- 4 counter with an input clock frequency of 1500 Hz has an output frequency of 375 Hz.

A major advantage of the synchronous counter over the nonsynchronous counter is its ability to:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 7: Counters and Registers

A 30 kHz clock pulse is applied to a MOD- 15 ripple counter. What is the output frequency?

A MOD 12 and a MOD 10 counter are cascaded. The input clock frequency is 60 MHz. Determine the counter output frequency.

-Select the sequence for the counter in Figure 7- 1 that best describes its operation.

When two counters are cascaded, the overall MOD number is equal to the____of their individual MOD numbers

MOD number = 2n, where n = number of flip- flops.

-What will the display reading in Figure 7- 1 be if the sampling interval is 100 ms and the unknown frequency is 200 kHz? (Assume the counter was cleared prior to the sampling interval.)

-The "CLEAR" input in Figure 7- 1:

Typically, four flip- flops are required for a MOD- 60 counter.

The + sign on a counter symbol by the input labeled CP indicates a count- up operation.

Table 7- 1 Table 7- 1 shows a state sequence used to program a GAL16V as a counter. The indicated sequence represents a:

Asynchronous down counters:

Shift registers that are identified as parallel in/parallel out, serial in/parallel out, etc. are defined in this manner because:

How many stages would be required for a cascaded BCD counter to provide a decimal count of 9,999?

A MOD- 4 counter with an input clock frequency of 1500 Hz has an output frequency of 375 Hz.

A major advantage of the synchronous counter over the nonsynchronous counter is its ability to:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

MOD number = 2ⁿ, where n = number of flip- flops.