Question 1

All flip- flops change states at the same time in an asynchronous counter.

Accepted Answer

A) True 
 B)False

Question 2

For a pulse waveform, tw stands for ____.

Accepted Answer

Question 3

Which of the following is TRUE regarding asynchronous counters?

Accepted Answer

A)  propagation delay is increased 
B)  J and K inputs are permanently high on LSB flip- flop 
C)  less circuitry required than synchronous counters 
D)  J and K inputs must be decoded on the LSB 
A)  propagation delay is increased 
B)  J and K inputs are permanently high on LSB flip- flop 
C)  less circuitry required than synchronous counters 
D)  J and K inputs must be decoded on the LSB

Question 4

Duty cycle is the ratio of ____	to____.

Accepted Answer

The answer of Duty cycle is the ratio of ____	to____....

Question 5

An asynchronous IC counter has clock inputs labeled  and  . The overbars indicate the clock inputs are activated by a:

Accepted Answer

A)  PGT. 
B)  NGT. 
A)  PGT. 
B)  NGT.

Question 6

The primary difference between a 3- bit up- counter and a 3- bit down- counter is:

Accepted Answer

A)  An up counter's output decreases by one with each input clock pulse whereas a down counter's output increases by one with each input clock pulse. 
B)  An up counter's output increases by one with each input clock pulse whereas a down counter's output decreases by one with each input clock pulse. 
C)  In a normal count sequence, a 000 is followed by 001 (in an up- counter) and by 111 (in a down- counter). 
D)  Both B and C 
E)  Both A and C 
A)  An up counter's output decreases by one with each input clock pulse whereas a down counter's output increases by one with each input clock pulse. 
B)  An up counter's output increases by one with each input clock pulse whereas a down counter's output decreases by one with each input clock pulse. 
C)  In a normal count sequence, a 000 is followed by 001 (in an up- counter) and by 111 (in a down- counter). 
D)  Both B and C 
E)  Both A and C

Question 7

A counter whose MOD N will have a 50% duty cycle.

Accepted Answer

A) True 
 B)False

Question 8

A common characteristic of ALL shift- register counters is:

Accepted Answer

A)  they use fewer flip- flops than binary counters. 
B)  they require more decoding gates than do binary counters. 
C)  they all use feedback where the last flip- flop output is someway connected back to the first flip- flop. 
D)  they count in true binary form. 
A)  they use fewer flip- flops than binary counters. 
B)  they require more decoding gates than do binary counters. 
C)  they all use feedback where the last flip- flop output is someway connected back to the first flip- flop. 
D)  they count in true binary form.

Question 9

A single BCD counter counts from 0 to ____and then recycles to 0.

Accepted Answer

The answer of A single BCD counter counts from 0...

Question 10

A primary advantage of using J- K flip- flops in asynchronous counter circuits is their ability to:

Accepted Answer

A)  toggle on the clock if the J- K inputs are held HIGH. 
B)  toggle on the clock if the PRESET and CLEAR inputs are held LOW. 
C)  toggle on the clock if the PRESET and CLEAR inputs are held HIGH. 
D)  toggle on the clock if the J- K inputs are held LOW. 
A)  toggle on the clock if the J- K inputs are held HIGH. 
B)  toggle on the clock if the PRESET and CLEAR inputs are held LOW. 
C)  toggle on the clock if the PRESET and CLEAR inputs are held HIGH. 
D)  toggle on the clock if the J- K inputs are held LOW.

Question 11

A counter that counts from 0000 to 1111 is called a MOD- 16 counter.

Accepted Answer

A) True 
 B)False

Question 12

The asynchronous presetting of parallel counters to a specific count normally requires the use of the:

Accepted Answer

A)  clock and the J- K inputs. 
B)    and the J- K inputs. 
C)  clock, PRESET, and CLEAR inputs. 
D)   , PRESET, and CLEAR inputs. 
A)  clock and the J- K inputs. 
B)    and the J- K inputs. 
C)  clock, PRESET, and CLEAR inputs. 
D)   , PRESET, and CLEAR inputs.

Question 13

A MOD- 10 counter is also referred to as a decade counter.

Accepted Answer

A) True 
 B)False

Question 14

Which group of logic devices represents the minimum hardware required for a MOD 64 synchronous counter?

Accepted Answer

A)  five flip- flops, three AND gates 
B)  four flip- flops, two AND gates 
C)  six flip- flops, four AND gates 
D)  seven flip- flops, five AND gates 
A)  five flip- flops, three AND gates 
B)  four flip- flops, two AND gates 
C)  six flip- flops, four AND gates 
D)  seven flip- flops, five AND gates

Question 15

A reliable method for eliminating decoder spikes is to use a technique called____.

Accepted Answer

The answer of A reliable method for eliminating decoder spikes...

Question 16

The process of designing a synchronous counter that will count in a nonbinary sequence is primarily based on:

Accepted Answer

A)  modifying asynchronous counters to change states on every second input clock pulse. 
B)  modifying BCD counters to change states on every second input clock pulse. 
C)  elimination of the counter stages and the addition of combinatorial logic circuits to produce the desired counts. 
D)  external logic circuits that decode the various states of the counter to apply the correct logic levels to the J- K inputs. 
A)  modifying asynchronous counters to change states on every second input clock pulse. 
B)  modifying BCD counters to change states on every second input clock pulse. 
C)  elimination of the counter stages and the addition of combinatorial logic circuits to produce the desired counts. 
D)  external logic circuits that decode the various states of the counter to apply the correct logic levels to the J- K inputs.

Question 17

BCD counters usually have their count displayed on 7- segment displays.

Accepted Answer

A) True 
 B)False

Question 18

A parallel in/parallel out register normally has data inputs loaded 	and data outputs transferred ____.

Accepted Answer

A)  asynchronously, asynchronously 
B)  synchronously, synchronously 
C)  synchronously, asynchronously 
D)  asynchronously, synchronously 
A)  asynchronously, asynchronously 
B)  synchronously, synchronously 
C)  synchronously, asynchronously 
D)  asynchronously, synchronously

Question 19

A MOD- 5 counter would count to a maximum of 101 and then clear to recycle.

Accepted Answer

A) True 
 B)False

Question 20

Karnaugh mapping is the preferred method to design logic circuits from an excitation diagram. Sum of product expressions can be formed directly from excitation tables. For J = X; K = X conditions:

Accepted Answer

A)  do not form SOP expressions for X inputs. 
B)  X must be treated as a 0. 
C)  X must be treated as a 1. 
D)  any of the above 
A)  do not form SOP expressions for X inputs. 
B)  X must be treated as a 0. 
C)  X must be treated as a 1. 
D)  any of the above

All flip- flops change states at the same time in an asynchronous counter.

For a pulse waveform, t_wstands for ____.

Which of the following is TRUE regarding asynchronous counters?

Duty cycle is the ratio of to.

An asynchronous IC counter has clock inputs labeled and . The overbars indicate the clock inputs are activated by a:

The primary difference between a 3- bit up- counter and a 3- bit down- counter is:

A counter whose MOD < 2^Nwill have a 50% duty cycle.

A common characteristic of ALL shift- register counters is:

A single BCD counter counts from 0 to ____and then recycles to 0.

A primary advantage of using J- K flip- flops in asynchronous counter circuits is their ability to:

A counter that counts from 0000 to 1111 is called a MOD- 16 counter.

The asynchronous presetting of parallel counters to a specific count normally requires the use of the:

A MOD- 10 counter is also referred to as a decade counter.

Which group of logic devices represents the minimum hardware required for a MOD 64 synchronous counter?

A reliable method for eliminating decoder spikes is to use a technique called____.

The process of designing a synchronous counter that will count in a nonbinary sequence is primarily based on:

BCD counters usually have their count displayed on 7- segment displays.

A parallel in/parallel out register normally has data inputs loaded and data outputs transferred ____.

A MOD- 5 counter would count to a maximum of 101 and then clear to recycle.

Karnaugh mapping is the preferred method to design logic circuits from an excitation diagram. Sum of product expressions can be formed directly from excitation tables. For J = X; K = X conditions:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 7: Counters and Registers

All flip- flops change states at the same time in an asynchronous counter.

For a pulse waveform, tw stands for ____.

Which of the following is TRUE regarding asynchronous counters?

Duty cycle is the ratio of ____ to____.

An asynchronous IC counter has clock inputs labeled and . The overbars indicate the clock inputs are activated by a:

The primary difference between a 3- bit up- counter and a 3- bit down- counter is:

A counter whose MOD < 2N will have a 50% duty cycle.

A common characteristic of ALL shift- register counters is:

A single BCD counter counts from 0 to ____and then recycles to 0.

A primary advantage of using J- K flip- flops in asynchronous counter circuits is their ability to:

A counter that counts from 0000 to 1111 is called a MOD- 16 counter.

The asynchronous presetting of parallel counters to a specific count normally requires the use of the:

A MOD- 10 counter is also referred to as a decade counter.

Which group of logic devices represents the minimum hardware required for a MOD 64 synchronous counter?

A reliable method for eliminating decoder spikes is to use a technique called____.

The process of designing a synchronous counter that will count in a nonbinary sequence is primarily based on:

BCD counters usually have their count displayed on 7- segment displays.

A parallel in/parallel out register normally has data inputs loaded and data outputs transferred ____.

A MOD- 5 counter would count to a maximum of 101 and then clear to recycle.

Karnaugh mapping is the preferred method to design logic circuits from an excitation diagram. Sum of product expressions can be formed directly from excitation tables. For J = X; K = X conditions:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

For a pulse waveform, t_wstands for ____.

Duty cycle is the ratio of to.

A counter whose MOD < 2^Nwill have a 50% duty cycle.