Question 1

The megafunction LPM_SHIFTREG is found in the MegaWizard Manager's ____ folder.

Accepted Answer

The answer of The megafunction LPM_SHIFTREG is found in the...

Question 2

Data from a ____out 6- bit register could be loaded onto a data bus in one clock pulse.

Accepted Answer

The answer of Data from a ____out 6- bit register...

Question 3

The decoding gates for asynchronous counters may have "glitches" on their outputs because:

Accepted Answer

A)  the flip- flops change states one at a time and erroneous counts may occur prior to the time all FF outputs have stabilized. 
B)  the flip- flops all change states at the same time but tpd may vary slightly for each FF thereby producing glitches. 
C)  the flip- flops change states one at a time; therefore no change for producing a glitch will ever exist. 
D)  the flip- flops all change states at the same time. 
A)  the flip- flops change states one at a time and erroneous counts may occur prior to the time all FF outputs have stabilized. 
B)  the flip- flops all change states at the same time but tpd may vary slightly for each FF thereby producing glitches. 
C)  the flip- flops change states one at a time; therefore no change for producing a glitch will ever exist. 
D)  the flip- flops all change states at the same time.

Question 4

The propagation delay in individual stages of an asynchronous counter is cumulative.

Accepted Answer

A) True 
 B)False

Question 5

The best way to eliminate decoding glitches in asynchronous counters is to:

Accepted Answer

A)  use a strobe signal to disable the decoding AND gates until the flip- flops reach a stable state in response to a clock pulse. 
B)  use a strobe signal to disable the counter flip- flops until a time greater than N (tpd) has elapsed. 
C)  use a strobe signal to enable the decoding AND gates until the flip- flops reach a stable state in response to a clock pulse. 
D)  use a strobe signal to enable the counter flip- flops until a time greater than N (tpd) has elapsed. 
A)  use a strobe signal to disable the decoding AND gates until the flip- flops reach a stable state in response to a clock pulse. 
B)  use a strobe signal to disable the counter flip- flops until a time greater than N (tpd) has elapsed. 
C)  use a strobe signal to enable the decoding AND gates until the flip- flops reach a stable state in response to a clock pulse. 
D)  use a strobe signal to enable the counter flip- flops until a time greater than N (tpd) has elapsed.

Question 6

The MOD- 10 counter is also referred to as a ____	counter.

Accepted Answer

The answer of The MOD- 10 counter is also referred...

Question 7

One potential problem with asynchronous counters is that the overall propagation delay increases with each added flip- flop.

Accepted Answer

A) True 
 B)False

Question 8

A MOD- 16 ripple counter is holding the count 10112. What will the count be after 31 clock pulses?

Accepted Answer

A)  10012  
B)  10102  
C)  11002  
D)  10112 
A)  10012  
B)  10102  
C)  11002  
D)  10112

Question 9

Synchronous (parallel) counters do not experience the delay problems encountered with asynchronous (ripple) counters because:

Accepted Answer

A)  the input clock pulses are applied only to the last stage. 
B)  the input clock pulses are applied simultaneously to each stage. 
C)  the input clock pulses are not used to activate any of the counter stages. 
D)  the input clock pulses are applied only to the first and last stage. 
A)  the input clock pulses are applied only to the last stage. 
B)  the input clock pulses are applied simultaneously to each stage. 
C)  the input clock pulses are not used to activate any of the counter stages. 
D)  the input clock pulses are applied only to the first and last stage.

Question 10

A MOD- 8 asynchronous counter has a "worst case" propagation delay of tphl = 37 ns. The maximum input clock frequency for this counter would be:

Accepted Answer

A)  6.756 MHz 
B)  13.514 MHz 
C)  9.009 MHz 
D)  5.405 MHz 
A)  6.756 MHz 
B)  13.514 MHz 
C)  9.009 MHz 
D)  5.405 MHz

Question 11

A digital clock requires a clock input that cycles once each second ( f = 1 Hz). The 60 Hz line voltage can be processed through a Schmitt trigger and a ____	counter to provide the 1 Hz clock signal.

Accepted Answer

The answer of A digital clock requires a clock input...

Question 12

Synchronous counters require less circuitry than asynchronous counters.

Accepted Answer

A) True 
 B)False

Question 13

When designing a digital clock system using 60 Hz line frequency, the first two major stages should include:

Accepted Answer

A)  a pulse shaper circuit and a BCD counter. 
B)  a pulse shaper circuit and a MOD 60 counter. 
C)  a MOD 60 counter and BCD counter. 
D)  a MOD 2 and BCD counter. 
A)  a pulse shaper circuit and a BCD counter. 
B)  a pulse shaper circuit and a MOD 60 counter. 
C)  a MOD 60 counter and BCD counter. 
D)  a MOD 2 and BCD counter.

Question 14

The procedure to design sequences that cycle over and over begins by examination of a(n)____ table to understand the logic needed at the J and K inputs.

Accepted Answer

The answer of The procedure to design sequences that cycle...

Question 15

A MOD- 32 synchronous counter requires:

Accepted Answer

A)  5 Flip- flops, 5 inverters, and 3 AND gates. 
B)  4 Flip- flops, 2 AND gates, and 4 inverters. 
C)  5 Flip- flops, 2 AND gates, and 3 inverters. 
D)  5 Flip- flops 2 AND gates, and 4 inverters. 
A)  5 Flip- flops, 5 inverters, and 3 AND gates. 
B)  4 Flip- flops, 2 AND gates, and 4 inverters. 
C)  5 Flip- flops, 2 AND gates, and 3 inverters. 
D)  5 Flip- flops 2 AND gates, and 4 inverters.

Question 16

The highest stable count that a MOD 24 counter could produce would be:

Accepted Answer

A)  2310  
B)  2410  
C)  2510  
D)  2610 
A)  2310  
B)  2410  
C)  2510  
D)  2610

Question 17

Shift- register counters use____, which means that the output of the last FF in the register is connected back to the first FF in some way

Accepted Answer

The answer of Shift- register counters use____, which means that...

Question 18

A synchronous MOD- 64 counter has tpd = 14 ns for each flip- flop and tpd = 12 ns for each AND gate. What is the maximum safe frequency for this counter?

Accepted Answer

A)  38.45 MHz 
B)  83.33 MHz 
C)  500 MHz 
D)  71.43 MHz 
A)  38.45 MHz 
B)  83.33 MHz 
C)  500 MHz 
D)  71.43 MHz

Question 19

When using the MegaWizard to design a counter, all you need to do is select the desired  features, the number of bits, and the ____.

Accepted Answer

The answer of When using the MegaWizard to design a...

Question 20

An asynchronous, or____, counter is one where each FF output serves as the CLK	
 input source for the next FF.

Accepted Answer

The answer of An asynchronous, or____, counter is one where...

The megafunction LPM_SHIFTREG is found in the MegaWizard Manager's ____ folder.

Data from a ____out 6- bit register could be loaded onto a data bus in one clock pulse.

The decoding gates for asynchronous counters may have "glitches" on their outputs because:

The propagation delay in individual stages of an asynchronous counter is cumulative.

The best way to eliminate decoding glitches in asynchronous counters is to:

The MOD- 10 counter is also referred to as a ____ counter.

One potential problem with asynchronous counters is that the overall propagation delay increases with each added flip- flop.

A MOD- 16 ripple counter is holding the count 1011₂. What will the count be after 31 clock pulses?

Synchronous (parallel) counters do not experience the delay problems encountered with asynchronous (ripple) counters because:

A MOD- 8 asynchronous counter has a "worst case" propagation delay of t_phl= 37 ns. The maximum input clock frequency for this counter would be:

A digital clock requires a clock input that cycles once each second ( f = 1 Hz). The 60 Hz line voltage can be processed through a Schmitt trigger and a ____ counter to provide the 1 Hz clock signal.

Synchronous counters require less circuitry than asynchronous counters.

When designing a digital clock system using 60 Hz line frequency, the first two major stages should include:

The procedure to design sequences that cycle over and over begins by examination of a(n)____ table to understand the logic needed at the J and K inputs.

A MOD- 32 synchronous counter requires:

The highest stable count that a MOD 24 counter could produce would be:

Shift- register counters use____, which means that the output of the last FF in the register is connected back to the first FF in some way

A synchronous MOD- 64 counter has t_pd= 14 ns for each flip- flop and t_pd= 12 ns for each AND gate. What is the maximum safe frequency for this counter?

When using the MegaWizard to design a counter, all you need to do is select the desired features, the number of bits, and the ____.

An asynchronous, or____, counter is one where each FF output serves as the CLK input source for the next FF.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 7: Counters and Registers

The megafunction LPM_SHIFTREG is found in the MegaWizard Manager's ____ folder.

Data from a ____out 6- bit register could be loaded onto a data bus in one clock pulse.

The decoding gates for asynchronous counters may have "glitches" on their outputs because:

The propagation delay in individual stages of an asynchronous counter is cumulative.

The best way to eliminate decoding glitches in asynchronous counters is to:

The MOD- 10 counter is also referred to as a ____ counter.

One potential problem with asynchronous counters is that the overall propagation delay increases with each added flip- flop.

A MOD- 16 ripple counter is holding the count 10112. What will the count be after 31 clock pulses?

Synchronous (parallel) counters do not experience the delay problems encountered with asynchronous (ripple) counters because:

A MOD- 8 asynchronous counter has a "worst case" propagation delay of tphl = 37 ns. The maximum input clock frequency for this counter would be:

A digital clock requires a clock input that cycles once each second ( f = 1 Hz). The 60 Hz line voltage can be processed through a Schmitt trigger and a ____ counter to provide the 1 Hz clock signal.

Synchronous counters require less circuitry than asynchronous counters.

When designing a digital clock system using 60 Hz line frequency, the first two major stages should include:

The procedure to design sequences that cycle over and over begins by examination of a(n)____ table to understand the logic needed at the J and K inputs.

A MOD- 32 synchronous counter requires:

The highest stable count that a MOD 24 counter could produce would be:

Shift- register counters use____, which means that the output of the last FF in the register is connected back to the first FF in some way

A synchronous MOD- 64 counter has tpd = 14 ns for each flip- flop and tpd = 12 ns for each AND gate. What is the maximum safe frequency for this counter?

When using the MegaWizard to design a counter, all you need to do is select the desired features, the number of bits, and the ____.

An asynchronous, or____, counter is one where each FF output serves as the CLK input source for the next FF.

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

A MOD- 16 ripple counter is holding the count 1011₂. What will the count be after 31 clock pulses?

A MOD- 8 asynchronous counter has a "worst case" propagation delay of t_phl= 37 ns. The maximum input clock frequency for this counter would be:

A synchronous MOD- 64 counter has t_pd= 14 ns for each flip- flop and t_pd= 12 ns for each AND gate. What is the maximum safe frequency for this counter?