A MOD 16 synchronous counter has inputs , PO, P1, P2, and P3. These inputs would most probably be used to:

A) reset the counter to 000O2 at the end of each count cycle. B) reset the counter to 00002 anytime P0- P3 is active HIGH and is active LOW. C) preset the counter to a value determined by the P0- P3 inputs anytime is active HIGH. D) preset the counter to a value determined by the P0- P3 inputs anytime is active LOW. A) reset the counter to 000O2 at the end of each count cycle. B) reset the counter to 00002 anytime P0- P3 is active HIGH and is active LOW. C) preset the counter to a value determined by the P0- P3 inputs anytime is active HIGH. D) preset the counter to a value determined by the P0- P3 inputs anytime is active LOW. D

Exam 7: Counters and Registers

An 8- bit counter is wired as follows: The CLK input to the first stage (LSB) is the system clock. Each stage's output is used as the CLK input to the next higher stage. This counter is a:

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(Multiple Choice)

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Question 1

Correct Answer:

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How many AND gates would be required to completely decode all the states of a MOD- 64 counter and how many inputs must each AND gate have?

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Question 2

Correct Answer:

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A MOD 16 synchronous counter has inputs labeled, PO, P₁, P₂, and P₃. These inputs would most probably be used to:

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Question 3

Correct Answer:

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A basic principle of operation of the synchronous counter is:

(Multiple Choice)

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Question 4

-The AND gate of Figure 7- 1 has a HIGH output only when:

(Multiple Choice)

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Question 5

The Q output from a JK flip- flop toggles on each clock input cycle as long as J = K = 1.

(True/False)

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Question 6

For any counter, the output from the last FF divides the input clock frequency by the____ number of the counter

(Short Answer)

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Question 7

-A 4096 Hz signal is applied to the "unknown frequency" input in Figure 7- 1. The sampling interval is 20 ms. Determine the display reading after the sampling interval. (Assume the counter had been cleared prior to the sampling interval.)

(Multiple Choice)

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Question 8

Generally speaking, a synchronous counter requires more circuitry than a comparable asynchronous counter.

(True/False)

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Question 9

In asynchronous counters made of JK flip- flops, the main clock signal is fed into the CLK input of the most significant flip- flop.

(True/False)

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Question 10

A production plant needs a counter that will count 4,000 items before resetting and recycling. How many flip- flop stages would this counter require?

(Multiple Choice)

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Question 11

AND gates are being used to decode active- HIGH outputs from a MOD- 16 counter. An LED is to come on only when the count equals 13₁₀. Assuming the D output is the MSB, the AND gate used to control the LED must have inputs of:

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Question 12

____counters are often used whenever pulses are to be counted and the results are displayed in decimal.

(Short Answer)

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Question 13

A MOD- 10 counter resets at 1010, thereby never actually reaching 10.

(True/False)

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Question 14

All decade counters are BCD counters.

(True/False)

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Question 15

The type of counter where each flip- flop provides the CLK input to the next flip- flop is referred to as a_____counter.

(Multiple Choice)

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Question 16

What type of register accepts data inputs one bit at a time and outputs all its data bits at the same time?

(Multiple Choice)

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Question 17

Select the response that best defines the use of the Master Reset (MR) on typical counter ICs.

(Multiple Choice)

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Question 18

The MOD number of a Johnson counter always equals one- half the number of flip- flops in the counter.

(True/False)

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Question 19

A state transition diagram for designing a synchronous nonbinary counter should include:

(Multiple Choice)

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Question 20

Showing 1 - 20 of 75

An 8- bit counter is wired as follows: The CLK input to the first stage (LSB) is the system clock. Each stage's output is used as the CLK input to the next higher stage. This counter is a:

How many AND gates would be required to completely decode all the states of a MOD- 64 counter and how many inputs must each AND gate have?

A MOD 16 synchronous counter has inputs labeled, PO, P₁, P₂, and P₃. These inputs would most probably be used to:

A basic principle of operation of the synchronous counter is:

-The AND gate of Figure 7- 1 has a HIGH output only when:

The Q output from a JK flip- flop toggles on each clock input cycle as long as J = K = 1.

For any counter, the output from the last FF divides the input clock frequency by the____ number of the counter

-A 4096 Hz signal is applied to the "unknown frequency" input in Figure 7- 1. The sampling interval is 20 ms. Determine the display reading after the sampling interval. (Assume the counter had been cleared prior to the sampling interval.)

Generally speaking, a synchronous counter requires more circuitry than a comparable asynchronous counter.

In asynchronous counters made of JK flip- flops, the main clock signal is fed into the CLK input of the most significant flip- flop.

A production plant needs a counter that will count 4,000 items before resetting and recycling. How many flip- flop stages would this counter require?

AND gates are being used to decode active- HIGH outputs from a MOD- 16 counter. An LED is to come on only when the count equals 13₁₀. Assuming the D output is the MSB, the AND gate used to control the LED must have inputs of:

____counters are often used whenever pulses are to be counted and the results are displayed in decimal.

A MOD- 10 counter resets at 1010, thereby never actually reaching 10.

All decade counters are BCD counters.

The type of counter where each flip- flop provides the CLK input to the next flip- flop is referred to as a_____counter.

What type of register accepts data inputs one bit at a time and outputs all its data bits at the same time?

Select the response that best defines the use of the Master Reset (MR) on typical counter ICs.

The MOD number of a Johnson counter always equals one- half the number of flip- flops in the counter.

A state transition diagram for designing a synchronous nonbinary counter should include:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 7: Counters and Registers

An 8- bit counter is wired as follows: The CLK input to the first stage (LSB) is the system clock. Each stage's output is used as the CLK input to the next higher stage. This counter is a:

How many AND gates would be required to completely decode all the states of a MOD- 64 counter and how many inputs must each AND gate have?

A MOD 16 synchronous counter has inputs labeled, PO, P1, P2, and P3. These inputs would most probably be used to:

A basic principle of operation of the synchronous counter is:

-The AND gate of Figure 7- 1 has a HIGH output only when:

The Q output from a JK flip- flop toggles on each clock input cycle as long as J = K = 1.

For any counter, the output from the last FF divides the input clock frequency by the____ number of the counter

-A 4096 Hz signal is applied to the "unknown frequency" input in Figure 7- 1. The sampling interval is 20 ms. Determine the display reading after the sampling interval. (Assume the counter had been cleared prior to the sampling interval.)

Generally speaking, a synchronous counter requires more circuitry than a comparable asynchronous counter.

In asynchronous counters made of JK flip- flops, the main clock signal is fed into the CLK input of the most significant flip- flop.

A production plant needs a counter that will count 4,000 items before resetting and recycling. How many flip- flop stages would this counter require?

AND gates are being used to decode active- HIGH outputs from a MOD- 16 counter. An LED is to come on only when the count equals 1310. Assuming the D output is the MSB, the AND gate used to control the LED must have inputs of:

____counters are often used whenever pulses are to be counted and the results are displayed in decimal.

A MOD- 10 counter resets at 1010, thereby never actually reaching 10.

All decade counters are BCD counters.

The type of counter where each flip- flop provides the CLK input to the next flip- flop is referred to as a_____counter.

What type of register accepts data inputs one bit at a time and outputs all its data bits at the same time?

Select the response that best defines the use of the Master Reset (MR) on typical counter ICs.

The MOD number of a Johnson counter always equals one- half the number of flip- flops in the counter.

A state transition diagram for designing a synchronous nonbinary counter should include:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Combinational Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

A MOD 16 synchronous counter has inputs labeled, PO, P₁, P₂, and P₃. These inputs would most probably be used to:

AND gates are being used to decode active- HIGH outputs from a MOD- 16 counter. An LED is to come on only when the count equals 13₁₀. Assuming the D output is the MSB, the AND gate used to control the LED must have inputs of: