Question 1

Each "1" in a K- map square represents:

Accepted Answer

A)  an input combination that results in a LOW output. 
B)  an input combination that results in a HIGH output. 
C)  an input combination that results in a DON'T CARE grouping. 
D)  None of the above. 
A)  an input combination that results in a LOW output. 
B)  an input combination that results in a HIGH output. 
C)  an input combination that results in a DON'T CARE grouping. 
D)  None of the above. B

Question 2

A "floating" TTL logic input will usually act like a(n):

Accepted Answer

A)  logic HIGH. 
B)  logic LOW. 
C)  active low input. 
D)  ground. 
A)  logic HIGH. 
B)  logic LOW. 
C)  active low input. 
D)  ground. A

Question 3

_______ circuits contain fewer than 12 gates per chip.

Accepted Answer

SSI

Question 4

Is it possible for a K- map to have two equally good solutions with each solution being dependent on how the 1s are looped?

Accepted Answer

A) True 
 B)False

Question 5

A logic probe indicates only a HIGH voltage level.

Accepted Answer

A) True 
 B)False

Question 6

For TTL devices, Vcc is nominally  _______ .

Accepted Answer

Question 7

The dependent notation =1 inside a block and a triangle on the output indicates a(n) _______  gate.

Accepted Answer

The answer of The dependent notation =1 inside a block...

Question 8

Exclusive OR and Exclusive NOR gates have  _______ inputs.

Accepted Answer

The answer of Exclusive OR and Exclusive NOR gates have...

Question 9

The goal in grouping K- map squares is to use the  _______ number of loops.

Accepted Answer

The answer of The goal in grouping K- map squares...

Question 10

A K- map indicates the output value for each possible combination of input values.

Accepted Answer

A) True 
 B)False

Question 11

Which of the following expressions accurately describes the Exclusive- OR function?

Accepted Answer

A)  X =  
B)  X =   
C)  X =  
D)  X =  
A)  X =  
B)  X =   
C)  X =  
D)  X =

Question 12

Select the statement that best describes the use of "Don't Care" conditions on a K- map.

Accepted Answer

A)  Don't Care conditions should never occur and should not be included in K- map simplification procedures. 
B)  Don't Care conditions may only be changed to 1s. 
C)  Don't Care conditions may be changed to either a 0 or a 1. 
D)  Don't Care conditions may only be changed to 0s. 
A)  Don't Care conditions should never occur and should not be included in K- map simplification procedures. 
B)  Don't Care conditions may only be changed to 1s. 
C)  Don't Care conditions may be changed to either a 0 or a 1. 
D)  Don't Care conditions may only be changed to 0s.

Question 13

Which of the following voltage ranges defines acceptable low- level input for a CMOS IC?

Accepted Answer

A)  2 - 5 V 
B)  0 - 1.5 V 
C)  0 - 2 V 
D)  0 - 0.8 V 
A)  2 - 5 V 
B)  0 - 1.5 V 
C)  0 - 2 V 
D)  0 - 0.8 V

Question 14

High- level logic compilers can receive input by all but what method?

Accepted Answer

A)  schematic capture 
B)  narrative descriptions 
C)  truth tables 
D)  Boolean equations 
A)  schematic capture 
B)  narrative descriptions 
C)  truth tables 
D)  Boolean equations

Question 15

The logic gate that produces a HIGH output whenever its two inputs are equal is the:

Accepted Answer

A)  Exclusive OR. 
B)  Exclusive NOR. 
C)  Neither A or B 
D)  Both A and B 
A)  Exclusive OR. 
B)  Exclusive NOR. 
C)  Neither A or B 
D)  Both A and B

Question 16

Which of the following statements accurately represents the two best methods of logic circuit simplification?

Accepted Answer

A)  Boolean algebra and Karnaugh mapping 
B)  Boolean algebra and actual circuit trial and error evaluation 
C)  Karnaugh mapping and circuit waveform analysis 
D)  Actual circuit trial and error evaluation and waveform analysis 
A)  Boolean algebra and Karnaugh mapping 
B)  Boolean algebra and actual circuit trial and error evaluation 
C)  Karnaugh mapping and circuit waveform analysis 
D)  Actual circuit trial and error evaluation and waveform analysis

Question 17

-Using Boolean algebra, the original expression for Table 4- 1 simplifies to:

Accepted Answer

A)  Z =   
B)  Z =   
C)  Z =   
D)  Z =   
A)  Z =   
B)  Z =   
C)  Z =   
D)  Z =

Question 18

The TTL family of IC chips is composed of:

Accepted Answer

A)  bipolar junction transistors. 
B)  discrete component unijunction transistors. 
C)  unipolar field- effect transistors. 
D)  discrete component bipolar junction transistors. 
A)  bipolar junction transistors. 
B)  discrete component unijunction transistors. 
C)  unipolar field- effect transistors. 
D)  discrete component bipolar junction transistors.

Question 19

The logic gates required to implement the logic circuit in the preceding question would be:

Accepted Answer

A)  an Exclusive NOR gate with inputs B1 and B2 whose output is fed, along with input A, to an AND gate. 
B)  an Exclusive OR gate with inputs B1 and B2 whose output, is fed along with input A, to an AND gate. 
C)  an Exclusive OR gate with inputs B1 and B2 whose output is fed, along with input A, to an OR gate. 
D)  an Exclusive NOR gate with inputs B1 and B2 whose output is fed, along with input A, to an OR gate. 
A)  an Exclusive NOR gate with inputs B1 and B2 whose output is fed, along with input A, to an AND gate. 
B)  an Exclusive OR gate with inputs B1 and B2 whose output, is fed along with input A, to an AND gate. 
C)  an Exclusive OR gate with inputs B1 and B2 whose output is fed, along with input A, to an OR gate. 
D)  an Exclusive NOR gate with inputs B1 and B2 whose output is fed, along with input A, to an OR gate.

Question 20

The truth table in Table 4- 1 indicates that:

Accepted Answer

A)  The output (Z) is HIGH only when the binary input count is an odd number. 
B)  The output (Z) is HIGH only when a single input is HIGH. 
C)  The output (Z) is HIGH only when the majority of the inputs are HIGH. 
D)  The output (Z) is HIGH only when the binary input count is an even number greater than zero. 
A)  The output (Z) is HIGH only when the binary input count is an odd number. 
B)  The output (Z) is HIGH only when a single input is HIGH. 
C)  The output (Z) is HIGH only when the majority of the inputs are HIGH. 
D)  The output (Z) is HIGH only when the binary input count is an even number greater than zero.

Each "1" in a K- map square represents:

A "floating" TTL logic input will usually act like a(n):

_______ circuits contain fewer than 12 gates per chip.

Is it possible for a K- map to have two equally good solutions with each solution being dependent on how the 1s are looped?

A logic probe indicates only a HIGH voltage level.

For TTL devices, V_ccis nominally _______ .

The dependent notation =1 inside a block and a triangle on the output indicates a(n) _______ gate.

Exclusive OR and Exclusive NOR gates have _______ inputs.

The goal in grouping K- map squares is to use the _______ number of loops.

A K- map indicates the output value for each possible combination of input values.

Which of the following expressions accurately describes the Exclusive- OR function?

Select the statement that best describes the use of "Don't Care" conditions on a K- map.

Which of the following voltage ranges defines acceptable low- level input for a CMOS IC?

High- level logic compilers can receive input by all but what method?

The logic gate that produces a HIGH output whenever its two inputs are equal is the:

Which of the following statements accurately represents the two best methods of logic circuit simplification?

-Using Boolean algebra, the original expression for Table 4- 1 simplifies to:

The TTL family of IC chips is composed of:

The logic gates required to implement the logic circuit in the preceding question would be:

The truth table in Table 4- 1 indicates that:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

Exam 4: Combinational Logic Circuits

Each "1" in a K- map square represents:

A "floating" TTL logic input will usually act like a(n):

_______ circuits contain fewer than 12 gates per chip.

Is it possible for a K- map to have two equally good solutions with each solution being dependent on how the 1s are looped?

A logic probe indicates only a HIGH voltage level.

For TTL devices, Vcc is nominally _______ .

The dependent notation =1 inside a block and a triangle on the output indicates a(n) _______ gate.

Exclusive OR and Exclusive NOR gates have _______ inputs.

The goal in grouping K- map squares is to use the _______ number of loops.

A K- map indicates the output value for each possible combination of input values.

Which of the following expressions accurately describes the Exclusive- OR function?

Select the statement that best describes the use of "Don't Care" conditions on a K- map.

Which of the following voltage ranges defines acceptable low- level input for a CMOS IC?

High- level logic compilers can receive input by all but what method?

The logic gate that produces a HIGH output whenever its two inputs are equal is the:

Which of the following statements accurately represents the two best methods of logic circuit simplification?

-Using Boolean algebra, the original expression for Table 4- 1 simplifies to:

The TTL family of IC chips is composed of:

The logic gates required to implement the logic circuit in the preceding question would be:

The truth table in Table 4- 1 indicates that:

Introductory Concepts

Number Systems and Codes

Describing Logic Circuits

Flip-Flops and Related Devices

Digital Arithmetic: Operations and Circuits

Counters and Registers

Integrated-Circuit Logic Families

MSI Logic Circuits

Digital System Projects Using HDL

Interfacing With the Analog World

Memory Devices

Programmable Logic Device Architectures

Filters

For TTL devices, V_ccis nominally _______ .