Figure 4 The spec sheet shows IS1U1B1GSS S1U1B0= 200 nA (max)at VS1U1B1GS S1U1B0= -15 V and VS1U1B1DS S1U1B0= 0 V. -Refer to Figure 4. Assume the voltage gain is 0.92. The power delivered to the load resistor is

A) 1.2 mW B) 2.7 mW C) 2.3 mW D) 1.4 mW A) 1.2 mW B) 2.7 mW C) 2.3 mW D) 1.4 mW A

Figure 4 The spec sheet shows IS1U1B1GSS S1U1B0= 200 nA (max)at VS1U1B1GS S1U1B0= -15 V and VS1U1B1DS S1U1B0= 0 V. -Refer to Figure 4. The input resistance, RIN, assuming maximum IGSS is

A) 8.1 M▲ B) 75 M▲ C) 8.8 M▲ D) 10 M▲ A) 8.1 M▲ B) 75 M▲ C) 8.8 M▲ D) 10 M▲

Figure 1 The equation for gS1U1B1m S1U1B0is given in (b). -Refer to Figure 1. If C2 were to open,

A) there would be a small ac output B) the ac load line would shift C) both A and B D) none of the above A) there would be a small ac output B) the ac load line would shift C) both A and B D) none of the above

Exam 9: Fet Amplifiers and Switching Circuits

Figure 4 The spec sheet shows I_GSS= 200 nA (max)at V_GS= -15 V and V_DS= 0 V. -Refer to Figure 4. Assume the voltage gain is 0.92. The power delivered to the load resistor is

Free

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Question 1

Correct Answer:

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To form an ac equivalent circuit for a FET amplifier, VDD is assumed to be open.

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Question 2

Correct Answer:

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False

Figure 7 -Refer to Figure 7. If both VA and VB are low (0), then both

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Question 3

Correct Answer:

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The transconductance of a FET depends on ID.

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Question 4

Compared to a mechanical relay, a solid- state relay

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Question 5

Figure 7 -Refer to Figure 7. The logic circuit represented is a

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Question 6

Assume a self- biased JFET amplifier has IGSS = 10 nA, VGS = 1 V, and RG = 10 M▲. The input resistance, RIN, of the amplifier is

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Question 7

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. Assume an unbypassed 36 ▲ resistor is inserted in series with RS. This primary effect of this change is to cause

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Question 8

Switched capacitors are used to emulate a

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Question 9

Figure 4 The spec sheet shows I_GSS= 200 nA (max)at V_GS= -15 V and V_DS= 0 V. -Refer to Figure 4. The input resistance, RIN, assuming maximum IGSS is

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Question 10

Figure 3 R_Sprovides feedback for bias stability -Refer to Figure 3. If you are troubleshooting the ac signal and find the output is three times larger than expected and clipped. This could be caused by

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Question 11

A common- drain (CD)amplifier is also called a source- follower.

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Question 12

In pulse width modulation, the output pulses are proportional to the

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Question 13

Figure 6 -Refer to Figure 6. This circuit is an example of

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Question 14

A common- gate (CG)amplifier has high input resistance.

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Question 15

Figure 3 R_Sprovides feedback for bias stability -Refer to Figure 3. Assume you are troubleshooting dc voltages with no signal input. You find that V_DD= V_D= 15 V. This could be caused by

(Multiple Choice)

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Question 16

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. If C2 were to open,

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Question 17

If a load resistor is connected to a CS amplifier the

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Question 18

In order to sample a waveform that is later reconstructed, the minimum sampling rate must be equal to

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Question 19

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. The specification sheet indicates that gm0 is 8500 µS and VGS(off)is -2.5 V. Assume VGS = -1 V. The expected gain, Av, is

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Question 20

Showing 1 - 20 of 36

Figure 4 The spec sheet shows I_GSS= 200 nA (max)at V_GS= -15 V and V_DS= 0 V. -Refer to Figure 4. Assume the voltage gain is 0.92. The power delivered to the load resistor is

To form an ac equivalent circuit for a FET amplifier, VDD is assumed to be open.

Figure 7 -Refer to Figure 7. If both VA and VB are low (0), then both

The transconductance of a FET depends on ID.

Compared to a mechanical relay, a solid- state relay

Figure 7 -Refer to Figure 7. The logic circuit represented is a

Assume a self- biased JFET amplifier has IGSS = 10 nA, VGS = 1 V, and RG = 10 M▲. The input resistance, RIN, of the amplifier is

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. Assume an unbypassed 36 ▲ resistor is inserted in series with RS. This primary effect of this change is to cause

Switched capacitors are used to emulate a

Figure 4 The spec sheet shows I_GSS= 200 nA (max)at V_GS= -15 V and V_DS= 0 V. -Refer to Figure 4. The input resistance, RIN, assuming maximum IGSS is

Figure 3 R_Sprovides feedback for bias stability -Refer to Figure 3. If you are troubleshooting the ac signal and find the output is three times larger than expected and clipped. This could be caused by

A common- drain (CD)amplifier is also called a source- follower.

In pulse width modulation, the output pulses are proportional to the

Figure 6 -Refer to Figure 6. This circuit is an example of

A common- gate (CG)amplifier has high input resistance.

Figure 3 R_Sprovides feedback for bias stability -Refer to Figure 3. Assume you are troubleshooting dc voltages with no signal input. You find that V_DD= V_D= 15 V. This could be caused by

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. If C2 were to open,

If a load resistor is connected to a CS amplifier the

In order to sample a waveform that is later reconstructed, the minimum sampling rate must be equal to

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. The specification sheet indicates that gm0 is 8500 µS and VGS(off)is -2.5 V. Assume VGS = -1 V. The expected gain, Av, is

Introduction to Semiconductors

Diodes and Applications

Special-Purpose Diodes

Bipolar Junction Transistors

Transistor Bias Circuits

BJT Amplifiers

BJT Power Amplifiers

Field-Effect Transistors Fets

Amplifier Frequency Response

Thyristors

The Operational Amplifier

Basic Op-Amp Circuits

Special-Purpose Integrated Circuits

Active Filters

Oscillators

Voltage Regulators

Communication Devices and Methods

Filters

Exam 9: Fet Amplifiers and Switching Circuits

Figure 4 The spec sheet shows IGSS = 200 nA (max)at VGS = -15 V and VDS = 0 V. -Refer to Figure 4. Assume the voltage gain is 0.92. The power delivered to the load resistor is

To form an ac equivalent circuit for a FET amplifier, VDD is assumed to be open.

Figure 7 -Refer to Figure 7. If both VA and VB are low (0), then both

The transconductance of a FET depends on ID.

Compared to a mechanical relay, a solid- state relay

Figure 7 -Refer to Figure 7. The logic circuit represented is a

Assume a self- biased JFET amplifier has IGSS = 10 nA, VGS = 1 V, and RG = 10 M▲. The input resistance, RIN, of the amplifier is

Figure 1 The equation for gm is given in (b). -Refer to Figure 1. Assume an unbypassed 36 ▲ resistor is inserted in series with RS. This primary effect of this change is to cause

Switched capacitors are used to emulate a

Figure 4 The spec sheet shows IGSS = 200 nA (max)at VGS = -15 V and VDS = 0 V. -Refer to Figure 4. The input resistance, RIN, assuming maximum IGSS is

Figure 3 RS provides feedback for bias stability -Refer to Figure 3. If you are troubleshooting the ac signal and find the output is three times larger than expected and clipped. This could be caused by

A common- drain (CD)amplifier is also called a source- follower.

In pulse width modulation, the output pulses are proportional to the

Figure 6 -Refer to Figure 6. This circuit is an example of

A common- gate (CG)amplifier has high input resistance.

Figure 3 RS provides feedback for bias stability -Refer to Figure 3. Assume you are troubleshooting dc voltages with no signal input. You find that VDD = VD = 15 V. This could be caused by

Figure 1 The equation for gm is given in (b). -Refer to Figure 1. If C2 were to open,

If a load resistor is connected to a CS amplifier the

In order to sample a waveform that is later reconstructed, the minimum sampling rate must be equal to

Figure 1 The equation for gm is given in (b). -Refer to Figure 1. The specification sheet indicates that gm0 is 8500 µS and VGS(off)is -2.5 V. Assume VGS = -1 V. The expected gain, Av, is

Introduction to Semiconductors

Diodes and Applications

Special-Purpose Diodes

Bipolar Junction Transistors

Transistor Bias Circuits

BJT Amplifiers

BJT Power Amplifiers

Field-Effect Transistors Fets

Amplifier Frequency Response

Thyristors

The Operational Amplifier

Basic Op-Amp Circuits

Special-Purpose Integrated Circuits

Active Filters

Oscillators

Voltage Regulators

Communication Devices and Methods

Filters

Figure 4 The spec sheet shows I_GSS= 200 nA (max)at V_GS= -15 V and V_DS= 0 V. -Refer to Figure 4. Assume the voltage gain is 0.92. The power delivered to the load resistor is

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. Assume an unbypassed 36 ▲ resistor is inserted in series with RS. This primary effect of this change is to cause

Figure 4 The spec sheet shows I_GSS= 200 nA (max)at V_GS= -15 V and V_DS= 0 V. -Refer to Figure 4. The input resistance, RIN, assuming maximum IGSS is

Figure 3 R_Sprovides feedback for bias stability -Refer to Figure 3. If you are troubleshooting the ac signal and find the output is three times larger than expected and clipped. This could be caused by

Figure 3 R_Sprovides feedback for bias stability -Refer to Figure 3. Assume you are troubleshooting dc voltages with no signal input. You find that V_DD= V_D= 15 V. This could be caused by

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. If C2 were to open,

Figure 1 The equation for g_mis given in (b). -Refer to Figure 1. The specification sheet indicates that gm0 is 8500 µS and VGS(off)is -2.5 V. Assume VGS = -1 V. The expected gain, Av, is